Task-Platzierung auf Many-Core-Prozessoren mit fehlerhaften Komponenten

This thesis describes the development and evaluation of three algorithms for the placement of parallelized applications on future many-core processors. The algorithms are able to compensate for permanent hardware faults and thereby cause a graceful degradation rather than a program crash. The fault model considers permanently failed cores, routers and processor interconnect links. The main goal of the placement algorithms is a working placement of applications, which consist of individual tasks communicating with each other, onto a many-core processor. The placement has to retain a high communication performance for each application. Since the algorithms are executed at the beginning of each program it is required that the runtime of the placement decision does not to grow excessively. Many-core processors and applications are modelled as graphs which depict the communication structures, as well as the intensities of the communications. Both synthetic task graphs and task graphs derived from real world applications are considered. This thesis develops the Connectivity-Sensitive Algorithm that generates static placements, which try to keep the distance between the tasks small. As a further refinement the Fitting Algorithm and the Favorite Neighbor Algorithm are presented. These two extensions to the basic algorithm are supposed to be beneficial in the placement of multiple task graphs and in the placement of task graphs with a strong imbalance of communication intensities. Also methods to extend the static placements by dynamic processes are presented, which require changes to the hardware and the general placement strategy. In a detailed evaluation chapter all aspects of the task placement on potentially faulty many-core processors are considered. Placement in both the error-free case, as well as placement assuming faulty hardware components is investigated. The effect of any error supported by the error model is first analyzed individually, before combinations of errors are considered. The results are compared and contrasted with those of a well known algorithm from the literature and two simple placement metrics. Different network topologies and the bandwidth constraints of the on-chip network are also discussed. It turns out that the described Connectivity-Sensitive Algorithm is in most cases able to generate the placements with the lowest communication overhead, and is also able to find valid placements in the presence of high error rates. The two extended algorithms are not able to generate better results.